Virage Logic Launches 'Silicon Aware IP' to Maximize Yield, Time-to-Volume at 130nm and Below
FREMONT, Calif., Jan. 24 /PRNewswire-FirstCall/ -- Long known as the technology leader in semiconductor Physical IP (intellectual property), particularly for 130-nanometer (nm) and below processes, Virage Logic Corporation (NASDAQ: VIRL) once again demonstrated its superior technology vision with today's announcement of its Silicon Aware IP(TM) initiative. Silicon Aware IP is Physical IP, such as memories, logic and I/Os, designed with embedded Infrastructure IP for test, diagnostics, repair, and yield enhancements. The result is IP that is high yielding and enables rapid time-to-volume at advanced process nodes. In addition, Silicon Aware IP results in much higher test quality and reliability. Today, Virage Logic believes it is the only IP provider to offer Silicon Aware IP, an example of which is its Self-Test and Repair (STAR) Memory System(TM). The company's Silicon Aware IP initiative calls for its entire product portfolio to become Silicon Aware IP over time.
"We build intimate knowledge of our Physical IP into our Infrastructure IP. The resulting Silicon Aware IP not only dramatically improves yield and time-to-volume, it also eliminates the need for designers to integrate and manage two separate IP entities," said Adam Kablanian, Virage Logic's CEO and president. "We've been working toward this vision since the introduction of our STAR Memory System in 2001. Today, with the success of more than 100 STAR Memory System customers as a proof point, and our developments in extending design-for-manufacturability (DFM) into our logic products, we are rapidly moving forward on our vision of offering an entire product portfolio of Silicon Aware IP."
The conventional approach uses independently optimized Infrastructure IP and Physical IP, in which case the IP cannot work together in the most beneficial manner. This approach results in marginal yield improvements and long time-to-volume. As design complexities increase at the more advanced process nodes of 130nm and below, this approach becomes even less effective. What's more, because this approach is "bolt-on," it negatively impacts the System-on-Chip's (SoC's) area, speed and power.
"In creating Silicon Aware IP, Virage Logic tunes its Infrastructure IP using specific knowledge of the Physical IP it will support, as well as the targeted manufacturing process. In turn, our Physical IP is created with an understanding of the test, diagnostics, reliability and yield improvement algorithms that are designed into the Infrastructure IP," noted Dr. Yervant Zorian, vice president and chief scientist, Virage Logic. "By using a single compiler to jointly generate the Infrastructure and Physical IP, designers can realize significant time savings. Additionally, because they are jointly architected, they share some of the same structures. This results in significant area, speed, power and most importantly, yield advantages."
About Virage Logic Corporation
Founded in 1996, Virage Logic Corporation rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Today the company is a global leader in semiconductor IP platforms comprising embedded memories, standard cells, and I/Os and is pioneering the development of a new class of IP called Silicon Aware IP. Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company's comprehensive quality efforts are validated in its FirstPass-Silicon Characterization Lab, which helps ensure high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit http://www.viragelogic.com/.
SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACT OF 1995:
Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to trends, business outlook, products, and customer relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic's ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic's ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic's technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company's ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company's Annual Report on Form 10-K for the period ended September 30, 2004, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic's website (http://www.viragelogic.com/) or from the SEC's website (http://www.sec.gov/), and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.
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CONTACT: Sabina Burns of Virage Logic Corporation, +1-510-743-8115, or
sabina.burns@viragelogic.com; or Kerry McClenahan of McClenahan Bruer
Communications, +1-503-546-1002, or kerry@mcbru.com, for Virage Logic
Corporation
Web site: http://www.viragelogic.com/
